Method of manufacturing lateral double-diffused metal oxide semiconductor device

ABSTRACT

A method of manufacturing an LDMOS transistor comprises providing a semiconductor substrate of a first conductivity type having a well region of a second conductivity type formed on a surface of the substrate. Ions of the first conductivity type are implanted into a part of the well region with a predetermined energy. The substrate is subjected to a heat treatment so that the implanted ions are diffused to form a diffusion region of the first conductivity type on the surface of the substrate. Then, a gate oxide layer and a gate electrode are formed on the surface of the substrate. Finally, a drain region is formed on the surface of the substrate. The predetermined energy for the implantation is set so that an accelerated oxidation during a formation of the gate oxide layer is inhibited.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a manufacturing method of anLDMOS transistor in which an ion-implantation process can be omitted.

[0002] A lateral double-diffused metal oxide semiconductor (LDMOS) isknown as a small-sized power device having a small power consumption,and a structure and manufacturing method of the semiconductor aredisclosed, for example, in Japanese Patent Application Laid-Open No.1998-335663. In general, there are N-type and P-type LDMOSs. Here, amanufacturing method of a conventional LDMOS will be describedhereinafter in terms of an example of the N-type.

[0003] Respective techniques such as oxidation, photolithography, andimpurity implantation are used to implant N-type impurities such asphosphorus (P) into a predetermined region on a P-type semiconductorsubstrate. Subsequently, a diffusion technique is used to form an N-typewell as a drain. Subsequently, techniques such as photolithography andion-implantation are used to implant P-type impurities such as boron (B)forming a D well of the LDMOS into the N-type well, then the same resistis used to implant the N-type impurities such as arsenic (As), and thediffusion technique is used to form a P-type diffusion layer forming theD well and an N-type diffusion layer forming a source. Here, since boron(B) is a small element and has a large diffusion coefficient as comparedwith arsenic (As), the P-type diffusion layer is formed to be deeperthan the N-type diffusion layer.

[0004] Subsequently, a LOCOS forming technique is used to form a fieldoxide film for isolating elements from one another, an oxidationtechnique is used to form a gate oxide film on an inner surface of thefield oxide film, and respective techniques such as known CVD,photolithography, and etching are used to form a polysilicon electrodein a channel forming region on the gate oxide film so that the electrodeextends over the N-type well, P-type diffusion layer forming the D well,and N-type diffusion layer.

[0005] Subsequently, the photolithography technique is used to perform adesired patterning, and the resist and gate electrode are used as masksto implant the N-type impurities such as phosphorus (P) into the surfacein the N-type well. Moreover, the diffusion technique is used to formthe N-type diffusion layer forming a reduced surface drain (RSD) in theN-type well on a region having no P-type diffusion layer forming the Dwell.

[0006] Subsequently, the photolithography and implantation techniquesare used to implant the N-type impurities such as arsenic (As) in aregion as a part of the N-type diffusion layer from which electrodes ofa drain and source are extracted, and implant the P-type impurities suchas boron (B) in a region from which the electrode of the D well isextracted. Furthermore, the diffusion technique is used to form theN-type and P-type diffusion layers, and finally the LDMOS is formedthrough contact formation, and wiring formation.

[0007] For the LDMOS formed by the aforementioned conventional method,after the N-type diffusion layer forming the source is formed, the gateoxide film is formed. Therefore, the gate oxide film on the N-typediffusion layer forming the source is formed to be thicker than the gateoxide film on the D well by accelerated oxidation. In this manner, astepped portion is formed in a boundary having a difference in thicknessin the gate oxide film in this manner. Therefore, an electric fielddistribution in the gate oxide film is not uniform, and there isuncertainty in reliability of pressure resistance of the gate oxidefilm.

SUMMARY OF THE INVENTION

[0008] The present invention may solve the aforementioned prior-artproblem and provide a highly reliable semiconductor device. In thedevice, an accelerated oxidation during formation of a gate oxide filmcould be suppressed. Further, a stepped portion of the gate oxide filmon a D well may be reduced.

[0009] A method of manufacturing an LDMOS transistor of the presentinvention comprises providing a semiconductor substrate of a firstconductivity type having a well region of a second conductivity typeformed on a surface of the substrate. Ions of the first conductivitytype are implanted into a part of the well region with a predeterminedenergy. The substrate is subjected to a heat treatment so that theimplanted ions are diffused to form a diffusion region of the firstconductivity type on the surface of the substrate. Then, a gate oxidelayer and a gate electrode are formed on the surface of the substrate.Finally, a drain region is formed on the surface of the substrate. Thepredetermined energy for the implantation is set so that an acceleratedoxidation during a formation of the gate oxide layer is inhibited.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIGS. 1(A) to 1(F) are transverse sectional front views showing amanufacturing process of an LDMOS transistor according to a firstembodiment of the present invention.

[0011] FIGS. 2(A) to 2(D) are transverse sectional front views showingthe manufacturing process of the LDMOS transistor according to a secondembodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] FIGS. 1(A) to 1(F) are diagrams showing a manufacturing method ofa semiconductor device according to a first embodiment of the presentinvention. A first diffusion layer (well) 103 of a second conductivitytype is formed on a portion of a semiconductor substrate 101 of a firstconductivity type. A field oxide film 102 for isolating elements fromone another can be formed using a known LOCOS forming technique, and amethod similar to the conventional method can be used in a process forforming the first diffusion layer 103 of the second conductivity type.(FIG. 1(A))

[0013] Subsequently, a first insulating film 104 is formed on thesemiconductor substrate 101 of the first conductivity type, and aportion on the first diffusion layer 103 of the second conductivity typeis opened (first opening). The first insulating film 104 is formed in athickness of about 5000 angstroms by a known oxidation technique.Subsequently, a known photolithography/etching technique is used to openthe first insulating film 104 in a region forming a D well, and a firstinsulating film 104 b is formed in about 200 angstroms by the knownoxidation technique.

[0014] Subsequently, a second diffusion layer (D well) 105 of the firstconductivity type is formed in a portion in the first diffusion layer103 of the second conductivity type via the first opening. The seconddiffusion layer 105 of the first conductivity type forming the D well isformed by implanting P-type impurities such as boron (B) by a knownion-implantation technique, and subsequently performing a heat treatmentin an N₂ gas atmosphere at 1000° C. for about 20 minutes by a knowndiffusion technique. (FIG. 1(B))

[0015] Subsequently, an impurity 106 of the second conductivity type setto be introduced inwards via a main surface of the second diffusionlayer 105 of the first conductivity type is introduced into the seconddiffusion layer 105 of the first conductivity type via the first opening(source). A known high-energy ion-implantation technique can be used informing a source region, and the N-type impurity 106 such as arsenic(As) is implanted with an energy amount of 500 keV, and a dosage ofabout 5.0×10¹⁵/cm². In this case, for an arsenic ion, a high-energyion-implantation is set so that a stepped portion of an oxide film isnot formed on the D well by the subsequent heat treatment duringformation of a gate oxide film and the arsenic ion is diffused to thesurface by the heat treatment. (FIG. 1(C))

[0016] Subsequently, the first insulating film 104 is removed, a secondinsulating film (gate oxide film) 107 is formed on the semiconductorsubstrate 101 of the first conductivity type, and the impurity 106 ofthe second conductivity type is activated to form a third diffusionlayer 108 of the second conductivity type. After the first insulatingfilms 104, 104 b are removed, the second insulating film 107 is formedin about 300 angstroms using the known oxidation technique. In thiscase, the impurity 106 of the second conductivity type introduced intothe region forming the source is diffused to the surface, and the thirddiffusion layer 108 of the second conductivity type is formed (FIG.1(D))

[0017] Subsequently, a gate electrode material is formed on the secondinsulating film 107, and a gate electrode 109 of LDMOS is formed andextended from a partial region of the third diffusion layer 108 of thesecond conductivity type at least onto the region of the seconddiffusion layer 105 of the first conductivity type excluding the thirddiffusion layer 108 of the second conductivity type. For the gateelectrode 109, for example, polysilicon is formed in a region forming achannel using the known CVD/photolithography/etching technique. A fourthdiffusion layer (RSD) 110 of the second conductivity type is formed in aregion excluding the second diffusion layer 105 of the firstconductivity type in the first diffusion layer 103 of the secondconductivity type. (FIG. 1(E))

[0018] Subsequently, a fifth diffusion layer 111 of the secondconductivity type is formed in a region on a side opposite to that ofthe second diffusion layer 105 of the first conductivity type via thefourth diffusion layer 110 of the second conductivity type in the firstdiffusion layer 103 of the second conductivity type. Additionally, asixth diffusion layer 112 of the second conductivity type is formed in aportion in the third diffusion layer 108 of the second conductivitytype.

[0019] Subsequently, the known photolithography technique is used toperform a desired patterning, and a resist and the gate electrode 109are used as masks to implant N-type impurities such as phosphorus (P)into the surface in the first diffusion layer 103. The fourth diffusionlayer 110 of the second conductivity type forming an RSD is formed bythe known diffusion technique.

[0020] Subsequently, a seventh diffusion layer 113 of the firstconductivity type is formed in a portion in the second diffusion layer105 of the first conductivity type and connected to the second diffusionlayer 105 of the first conductivity type. The known photolithography andimplantation techniques are used to implant the N-type impurities suchas arsenic (AS) in a region from which electrodes of the drain andsource are extracted with an energy amount of 60 keV, and a dosage ofabout 1.0×10¹⁵/cm². The P-type impurities such as boron (B) areimplanted in a region from which an electrode of the D well is extractedwith an energy amount of 30 keV, and a dosage of about 1.0×10¹⁵/cm².(FIG. 1(F))

[0021] Finally, the known diffusion technique is used to form the fifth,sixth, and seventh diffusion layers 111, 112, 113. Finally, after acontact and wiring are formed, the LDMOS is formed. Additionally, aknown technique is used in forming the contact and wiring (not shown).

[0022] A known semiconductor manufacturing technique can be used inrespective processes such as photolithography, etching, deposition ofvarious members, implantation, diffusion, contact formation, and wiringformation. This also applies to the following second embodiment of thepresent invention.

[0023] According to the first embodiment of the present invention, whenthe impurity of the second conductivity type forming the source regionis implanted by high-energy ion-implantation, accelerated oxidationduring formation of the gate oxide film can be suppressed, the steppedportion of the gate oxide film on the D well is reduced, and ahighly-reliable semiconductor device can be provided.

[0024] FIGS. 2(A) to 2(D) are process sectional views showing a secondembodiment of the present invention.

[0025] First, a first diffusion layer (well) 203 of the secondconductivity type is formed in a portion on a semiconductor substrate201 of the first conductivity type. Next, a first insulating film 204 isformed on the semiconductor substrate 201 of the first conductivitytype. A portion on the first diffusion layer 203 of the secondconductivity type is opened, and a first opening 204 a is formed. (FIG.2(A)) A second diffusion layer (D well) 205 of the first conductivitytype is formed in a portion in the first diffusion layer 203 of thesecond conductivity type via the first opening 204 a. (FIG. 2(A))

[0026] Subsequently, by the known photolithography and etchingtechniques, a resist 213 is formed, and in the first insulating film204, an opening 213 a is formed as a region from which the drainelectrode and source electrode of the LDMOS are extracted in a part of aregion in which the second diffusion layer 205 of the first conductivitytype is not formed in the first diffusion layer 203 of the secondconductivity type. The resist 213 is removed, and an impurity 206 of thesecond conductivity type set to be introduced inwards from a mainsurface of the semiconductor substrate 201 of the first conductivitytype and the second diffusion layer 205 of the first conductivity typesimultaneously via the second and first openings, so that the source anddrain are formed. (FIG. 2(B))

[0027] Here, by the known high-energy ion-implantation technique, theN-type impurities such as arsenic (As) are implanted with an energyamount of 500 keV, and a dosage of about 5.0×10¹⁵/cm². In this case, forthe implanted arsenic ion, the high-energy ion-implantation is set sothat the stepped portion of the oxide film on the D well is not formedby the subsequent heat treatment during formation of a gate oxide film207, and the arsenic ion is diffused to the surface by the heattreatment. (FIG. 2(C))

[0028] Subsequently, the first insulating film 204 is removed, thesecond insulating film (gate oxide film) 207 is formed on thesemiconductor substrate 201 of the first conductivity type, and theimpurity 206 of the second conductivity type is activated to form athird diffusion layer 208 of the second conductivity type.

[0029] Subsequently, the gate electrode material is formed on the secondinsulating film 207, and a gate electrode 209 of LDMOS is formed andextended from a partial region of the third diffusion layer 208 of thesecond conductivity type at least onto the region of the seconddiffusion layer 205 of the first conductivity type excluding the thirddiffusion layer 208 of the second conductivity type. Subsequently, afourth diffusion layer (RSD) 210 of the second conductivity type isformed in a region excluding the second diffusion layer 205 of the firstconductivity type in the first diffusion layer 203 of the secondconductivity type.

[0030] Subsequently, a sixth diffusion layer 212 of the firstconductivity type is formed in a portion in the second diffusion layer205 of the first conductivity type and connected to the second diffusionlayer 205 of the first conductivity type. (FIG. 2(D)).

[0031] The second embodiment is similar to the first embodiment in andafter a process of removing the first insulating film 204 and formingthe second insulating film (gate oxide film) 207.

[0032] According to the second embodiment of the present invention, inaddition to an effect of the first embodiment, there is an effect thatthe introduction of the impurity of the second conductivity type forforming the source region and the introduction of the impurity of thesecond conductivity type for extracting the drain and source electrodesare simultaneously performed, and an ion-implantation process cantherefore be reduced.

[0033] The preferred embodiments of the manufacturing method of theLDMOS transistor according to the present invention have been describedabove with reference to the accompanying drawings, but the presentinvention is not limited to these embodiments. A person skilled in theart would apparently develop various modifications within a category oftechnical thoughts defined by the appended claims, and suchmodifications are also deemed to be naturally within the technical scopeof the present invention.

[0034] As described above, according to the present invention, there canbe provided a highly reliable LDMOS transistor in which acceleratedoxidation during formation of the gate oxide film can be suppressed andtherefore the stepped portion of the gate oxide film on the D well isreduced.

What is claimed is:
 1. A method of manufacturing an LDMOS transistorcomprising: providing a semiconductor substrate of a first conductivitytype having a well region of a second conductivity type formed on asurface thereof; implanting ions of the first conductivity type into apart of the well region with a predetermined energy; subjecting thesubstrate to a heat treatment so that the implanted ions are diffused toform a diffusion region of the first conductivity type on the surface ofthe substrate; forming a gate oxide layer and a gate electrode on thesurface of the substrate; and forming a drain region on the surface ofthe substrate, wherein the predetermined energy is set so that anaccelerated oxidation during a formation of the gate oxide layer isinhibited.
 2. A method of manufacturing an LDMOS transistor according toclaim 1, wherein said implantation is conducted as a high energy ionimplantation.
 3. A method of manufacturing an LDMOS transistor accordingto claim 1, wherein the predetermined energy is about 500 KeV.
 4. Amethod of manufacturing an LDMOS transistor according to claim 1,wherein said implantation is conducted with a dosage of about5.0×10¹⁵/cm².
 5. A method of manufacturing an LDMOS transistor accordingto claim 1, wherein said implantation is conducted into a region thesubstrate where the drain region is formed.
 6. A method of manufacturingan LDMOS transistor according to claim 1, wherein the drain region is areduced surface drain.
 7. A method of manufacturing an LDMOS transistorcomprising: providing a semiconductor substrate of a first conductivitytype having a first well region of a second conductivity type formed ona surface thereof, and a second well region of the first conductivitytype formed within the first well; implanting ions of the secondconductivity type into a part of the second well region with apredetermined energy; subjecting the substrate to a heat treatment sothat the implanted ions are diffused to form a diffusion region of thesecond conductivity type on the surface of the substrate within thesecond well; forming a gate oxide layer and a gate electrode on thesurface of the substrate; and forming a drain region on the surface ofthe substrate, wherein the predetermined energy is set so that anaccelerated oxidation during a formation of the gate oxide layer isinhibited.
 8. A method of manufacturing an LDMOS transistor according toclaim 7, wherein said implantation is conducted as a high energy ionimplantation.
 9. A method of manufacturing an LDMOS transistor accordingto claim 7, wherein the predetermined energy is about 500 KeV.
 10. Amethod of manufacturing an LDMOS transistor according to claim 7,wherein said implantation is conducted with a dosage of about5.0×10¹⁵/cm².
 11. A method of manufacturing an LDMOS transistoraccording to claim 7, wherein said implantation is conducted into aregion the substrate where the drain region is formed.
 12. A method ofmanufacturing an LDMOS transistor according to claim 7, wherein thedrain region is a reduced surface drain.
 13. A method of manufacturingan LDMOS transistor comprising: providing a semiconductor substrate of afirst conductivity type having a first well of a second conductivitytype formed on a surface thereof within a first region, and a secondwell of the first conductivity type formed within a second region thatis inside of the first region; implanting ions of the secondconductivity type into the second well with a predetermined energy;subjecting the substrate to a heat treatment so that the implanted ionsare diffused to form a diffusion region of the second conductivity typelocated in a third region that is inside of the second region; forming agate oxide layer and a gate electrode on the surface of the substrate,the gate oxide layer extending from the first region to the third regionthrough the second region; and forming a drain region on the surface ofthe substrate within the first region, wherein the predetermined energyis set so that an accelerated oxidation during a formation of the gateoxide layer is inhibited.
 14. A method of manufacturing an LDMOStransistor according to claim 13, wherein said implantation is conductedas a high energy ion implantation.
 15. A method of manufacturing anLDMOS transistor according to claim 13, wherein the predetermined energyis about 500 KeV.
 16. A method of manufacturing an LDMOS transistoraccording to claim 13, wherein said implantation is conducted with adosage of about 5.0×10¹⁵/cm².
 17. A method of manufacturing an LDMOStransistor according to claim 13, wherein said implantation is conductedinto a region the substrate where the drain region is formed.
 18. Amethod of manufacturing an LDMOS transistor according to claim 13,wherein the drain region is a reduced surface drain.